A compact 1.1-Gb/s encoder and a memory-based 600-Mb/s decoder for LDPC convolutional codes

Authors:
Tyler L. Brandon;John C. Koob;Leendert Van Den Berg;Zhengang Chen;Amirhossein Alimohammad;Ramkrishna Swamy;Jason Klaus;Stephen Bates;Vincent C. Gaudet;Bruce F. Cockburn;Duncan G. Elliott
Affiliations:
Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada;Ukalta Engineering Corporation, Edmonton, AB, Canada;Raithlin Semiconductors, Inc., Canmore, AB, Canada;Ukalta Engineering Corporation, Edmonton, AB, Canada;Aptina Imaging, Inc., San Jose, CA;Google, Inc., San Jose, CA;Raithlin Semiconductors, Inc., Canmore, AB, Canada;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
Year:
2009

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Abstract

We present a rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder that we implemented in a 90-nm CMOS process. The 1.1-Gb/s encoder is a compact, low-power implementation that includes one-hot encoding for phase generation and built-in termination. The decoder design uses a memory-based interface with a minimum number of memory banks to deliver an information throughput of 1 b per clock cycle. The decoder shares one controller among a pipeline of decoder processors. The decoder dissipates 0.61 nJ of energy per decoded information bit at an SNR of 2 dB and a decoded throughput of 600 Mb/s. On-chip test circuitry permits accurate power measurements to be made at selectable SNR settings.