Jointly designed architecture-aware LDPC convolutional codes and high-throughput parallel encoders/decoders

Authors:
Zhengang Chen;Tyler L. Brandon;Duncan G. Elliott;Stephen Bates;Witold A. Krzymień;Bruce F. Cockburn
Affiliations:
Marvell Semiconductor, Inc., Santa Clara, CA;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada and TRLabs, Edmonton, AB, Canada;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2010

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Abstract

A novel design approach is proposed for low-density parity-check convolutional codes (LDPC-CCs), that jointly optimizes the code, encoder and decoder to achieve high-throughput parallel encoding and decoding. A series of implementation-oriented constraints are applied to construct architecture-aware (AA) codes by introducing algebraic structures into the parity-check matrix. The resulting AA codes have bit error rate performance comparable to other published LDPC-CCs. Given these AA LDPC-CCs, new architectures are proposed for a parallel LDPC-CC encoder with built-in termination and an LDPC-CC decoder that is parallel in the node dimension as well as pipelined in the iteration dimension. ASIC synthesis results for a 90-nm CMOS process show that the proposed encoder and the decoding processor achieve 2.0-Gbps throughputs at 250-MHz clock frequencies within silicon areas of 0.1 mm2 and 1 mm2 respectively.