A memory efficient partially parallel decoder architecture for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
High-throughput layered decoder implementation for quasi-cyclic LDPC codes
IEEE Journal on Selected Areas in Communications - Special issue on capaciyy approaching codes
An area-efficient and low-power multirate decoder for quasi-cyclic low-density parity-check codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory efficient multi-rate regular LDPC decoder for CMMB
IEEE Transactions on Consumer Electronics
A dual-rate LDPC decoder for china multimedia mobile broadcasting systems
IEEE Transactions on Consumer Electronics
High speed architectures for finding the first two maximum/minimum values
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a memory efficient architecture of layered decoder for the dual-rate LDPC codes in the China Multimedia Mobile Broadcasting (CMMB) system. An efficient scheme for reducing the memory block number is proposed to increase the memory usage efficiency, so that the quantity of memory bits, decoder area and power consumption is significantly reduced. At the same time, the memory structure keeps the ''one cycle one layer access'' timing schedule to achieve high decoding throughput. Furthermore, the early termination strategy is employed to further increase the throughput; a non-uniform quantization scheme and an area efficient calculation module are developed to further improve the memory efficiency and hardware resource efficiency, respectively. By using SMIC 130nm 1P7M CMOS process, the decoder is implemented and the core area is 5.29mm^2. The total memory bits consumption is only 130.5K which consumes 2.53mm^2 memory area.