A memory efficient parallel layered QC-LDPC decoder for CMMB systems
Integration, the VLSI Journal
| Hi-index | 0.43 |
This paper presents an efficient VLSI architecture and implementation for LDPC decoder used in China Multimedia Mobile Broadcasting (CMMB) systems. An area-efficient layered decoding architecture based on min-sum algorithm is incorporated in the design. A novel split-memory architecture is developed to efficiently handle the weight-2 submatrices that are rarely seen in conventional LDPC decoders. In addition, the check-node processing unit is highly optimized to minimize complexity and computing latency while facilitating a reconfigurable decoding core. The proposed design is implemented using 90 nm CMOS technology with the core area of approximately 4.4 mm2 and the standard supply voltage 1.0 V. The decoder can achieve the maximum throughput of 228 Mb/s for rate 1/2 and 342 Mb/s for rate 3/4 at 15 iterations of layered decoding. Therefore, it can be deployed on the CMMB mobile platform