Design methodology for IRA codes
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
The ten-year-old turbo codes are entering into service
IEEE Communications Magazine
The renaissance of Gallager's low-density parity-check codes
IEEE Communications Magazine
Low cost LDPC decoder for DVB-S2
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Disclosing the LDPC code decoder design space
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Implementing DSP Algorithms with On-Chip Networks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Low complexity LDPC code decoders for next generation standards
Proceedings of the conference on Design, automation and test in Europe
Non-fractional parallelism in LDPC decoder implementations
Proceedings of the conference on Design, automation and test in Europe
A memory efficient partially parallel decoder architecture for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Massive parallel LDPC decoding on GPU
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
Configurable LDPC Decoder Architectures for Regular and Irregular Codes
Journal of Signal Processing Systems
Low-complexity high-speed decoder design for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved layered min-sum decoding algorithm for low density parity check codes
MUSP'09 Proceedings of the 9th WSEAS international conference on Multimedia systems & signal processing
Fast convergence algorithm for decoding of low density parity check codes
WSEAS TRANSACTIONS on COMMUNICATIONS
Conflict resolution by matrix reordering for DVB-T2 LDPC decoders
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
A novel LDPC decoder for DVB-S2 IP
Proceedings of the Conference on Design, Automation and Test in Europe
Irregular designs for two-state systematic with serial concatenated parity codes
MILCOM'06 Proceedings of the 2006 IEEE conference on Military communications
Improvements on the design and implementation of DVB-S2 LDPC decoders
Computers and Electrical Engineering
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The new standard for digital video broadcast DVB-S2 features Low-Density Parity-Check (LDPC) codes as their channel coding scheme. The codes are defined for various code rates with a block size of 64800 which allows a transmission close to the theoretical limits. The decoding of LDPC is an iterative process. For DVB-S2 about 300000 messages are processed and reordered in each of the 30 iterations. These huge data processing and storage requirements are a real challenge for the decoder hardware realization, which has to fulfill the specified throughput of 255MBit/s for base station applications. In this paper we will show, to the best of our knowledge, the first published IP LDPC decoder core for the DVB-S2 standard. We present a synthesizable IP block based on ST Microelectronics 0:13µm CMOS technology.