Design methodology for IRA codes
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Synthesizable IP Core for DVB-S2 LDPC Code Decoding
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The renaissance of Gallager's low-density parity-check codes
IEEE Communications Magazine
Low complexity LDPC code decoders for next generation standards
Proceedings of the conference on Design, automation and test in Europe
Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder
Proceedings of the 45th annual Design Automation Conference
Efficient Helper Data Key Extractor on FPGAs
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A generic scalable architecture for min-sum/offset-min-sum unit for irregular/regular LDPC decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design space of flexible multigigabit LDPC decoders
VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
A network-on-chip-based turbo/LDPC decoder architecture
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The design of future communication systems with high throughput demands will become a critical task, especially when sophisticated channel coding schemes have to be applied. LDPC codes are one of the most promising candidates because of their outstanding communications performance. One major problem for a decoder hardware realization is the huge design space composed of many interrelated parameters which enforces drastic design trade-offs. Another important issue is the need for flexibility of such systems.In this paper we illuminate this design space with special emphasis on the strong interrelations of theses parameters. Three design studies are presented to highlight the effects on a generic architecture if some parameters are constraint by a given standard, given technology, and given area constraints.