The de Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI
IEEE Transactions on Computers
Fault-Tolerant Ring Embedding in de Bruijn Networks
IEEE Transactions on Computers
Implementing LDPC Decoding on Network-on-Chip
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
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IEEE Transactions on Parallel and Distributed Systems
Interconnection framework for high-throughput, flexible LDPC decoders
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Disclosing the LDPC code decoder design space
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding
Proceedings of the conference on Design, automation and test in Europe
Reliable network-on-chip based on generalized de Bruijn graph
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SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
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Proceedings of the great lakes symposium on VLSI
Flexible LDPC decoder architectures
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Design and implementation of an on-chip permutation network for multiprocessor system-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A network-on-chip-based turbo/LDPC decoder architecture
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper proposes a novel on-chip interconnection network adapted to a flexible multiprocessor LDPC decoder based on the de Bruijn network. The main characteristics of this network -- including its logarithmic diameter, scalable aggregate bandwidth, and optimized routing technique- allow it to efficiently support the communication intensive nature of the application. We present a detailed hardware implementation of the routers and the network interfaces as well as the packet format and the routing algorithm. The latter is a parallelized version of the shortest path with deflection routing algorithm. In order to evaluate the performance of the proposed network, a generic RTL VHDL description has been developed and synthesized with CMOS STMicroelectronics 0.18 μm technology. The flexibility and the scalability of this onchip communication network enable it to be used for any kind of LDPC code.