A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Disclosing the LDPC code decoder design space
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder
Proceedings of the 45th annual Design Automation Conference
On optimal and near-optimal turbo decoding using generalized max* operator
IEEE Communications Letters
Bit-level extrinsic information exchange method for double-binary turbo codes
IEEE Transactions on Circuits and Systems II: Express Briefs
Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
On chip interconnects for multiprocessor turbo decoding architectures
Microprocessors & Microsystems
A Flexible LDPC/Turbo Decoder Architecture
Journal of Signal Processing Systems
UDSM trends comparison: from technology roadmap to UltraSparc Niagara2
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The current convergence process in wireless technologies demands for strong efforts in the conceiving of highly flexible and interoperable equipments. This contribution focuses on one of the most important baseband processing units in wireless receivers, the forward error correction unit, and proposes a Network-on-Chip (NoC) based approach to the design of multi-standard decoders. High level modeling is exploited to drive the NoC optimization for a given set of both turbo and Low-Density-Parity-Check (LDPC) codes to be supported. Moreover, synthesis results prove that the proposed approach can offer a fully compliant WiMAX decoder, supporting the whole set of turbo and LDPC codes with higher throughput and an occupied area comparable or lower than previously reported flexible implementations. In particular, the mentioned design case achieves a worst-case throughput higher than 70 Mb/s at the area cost of 3.17 mm2 on a 90 nm CMOS technology.