VLSI architectures for turbo codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Scalable System Architecture for High-Throughput Turbo-Decoders
Journal of VLSI Signal Processing Systems
Low complexity LDPC code decoders for next generation standards
Proceedings of the conference on Design, automation and test in Europe
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
Low-complexity high-speed decoder design for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-throughput layered decoder implementation for quasi-cyclic LDPC codes
IEEE Journal on Selected Areas in Communications - Special issue on capaciyy approaching codes
Architecture-aware LDPC code design for multiprocessor software defined radio systems
IEEE Transactions on Signal Processing
Area-efficient high-throughput MAP decoder architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Highly-parallel decoding architectures for convolutional turbo codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Area-efficient high-speed decoding schemes for turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Iterative decoding of binary block and convolutional codes
IEEE Transactions on Information Theory
Interleavers for turbo codes using permutation polynomials over integer rings
IEEE Transactions on Information Theory
IEEE Journal on Selected Areas in Communications
A network-on-chip-based turbo/LDPC decoder architecture
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be required. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose a unified message passing algorithm for LDPC and Turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/Turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and Turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and Turbo codes with a low hardware overhead (about 15% area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/Turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/Turbo decoder has been synthesized on a TSMC 90 nm CMOS technology with a core area of 3.2 mm2. The decoder can support IEEE 802.16e LDPC codes, IEEE 802.11n LDPC codes, and 3GPP LTE Turbo codes. Running at 500 MHz clock frequency, the decoder can sustain up to 600 Mbps LDPC decoding or 450 Mbps Turbo decoding.