Energy efficient data transfer and storage organization for a MAP turbo decoder module
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Design of low-power high-speed maximum a priori decoder architectures
Proceedings of the conference on Design, automation and test in Europe
Architectures for Digital Signal Processing
Architectures for Digital Signal Processing
FPGA implementation of parallel turbo-decoders
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding
Proceedings of the conference on Design, automation and test in Europe
A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Reconfigurable turbo decoder with parallel architecture for 3GPP LTE system
IEEE Transactions on Circuits and Systems II: Express Briefs
A 150Mbit/s 3GPP LTE turbo code decoder
Proceedings of the Conference on Design, Automation and Test in Europe
A Flexible LDPC/Turbo Decoder Architecture
Journal of Signal Processing Systems
Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support
Journal of Signal Processing Systems
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The need for higher data rates is ever rising as wireless communications standards move from the third to the fourth generation. Turbo-Codes are the prevalent channel codes for wireless systems due to their excellent forward error correction capability. So far research has mainly focused on components of high throughput Turbo-Decoders. In this paper we explore the Turbo-Decoder design space anew, both under system design and deep-submicron implementation aspects.Our approach incorporates all levels of design, from I/O behavior down to floorplaning taking deep-submicron effects into account. Its scalability allows to derive optimized architectures tailored to the given throughput and target technology. We present results for 3GPP compliant Turbo-Decoders beyond 100 Mbit/s synthesized on a 0.18 μm standard cell library.