Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Guest Editors' Introduction: Application-Specific Microprocessors
IEEE Design & Test
Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Scalable System Architecture for High-Throughput Turbo-Decoders
Journal of VLSI Signal Processing Systems
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
From parallelism levels to a multi-ASIP architecture for turbo decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A design approach dedicated to network-based and conflict-free parallel interleavers
Proceedings of the great lakes symposium on VLSI
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This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory and communication interconnect scheme. This Application-Specific Instruction-set Processor has an SIMD architecture with a specialized and extensible instruction-set and 5-stages pipeline control. The attached memories and communication interfaces enable the design of efficient multiprocessor architectures. These multiprocessor architectures benefit from the recent shuffling technique introduced in the turbo-decoding field to reduce communication latency. The major characteristics of the proposed platform are its flexibility and scalability which make it reusable for various standards and operating modes. Results obtained for double binary DVB-RCS turbo codes demonstrate a 100 Mbit/s throughput using 16-ASIP multiprocessor architecture.