VLSI architectures for turbo codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Guest Editors' Introduction: Application-Specific Microprocessors
IEEE Design & Test
Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding
Proceedings of the conference on Design, automation and test in Europe
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
A rapid prototyping system for error-resilient multi-processor systems-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
A 150Mbit/s 3GPP LTE turbo code decoder
Proceedings of the Conference on Design, Automation and Test in Europe
Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parameterized area-efficient multi-standard turbo decoder
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A method of batching conflict routings in shuffle-exchange networks
Theoretical Computer Science
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Emerging digital communication applications and the underlying architectures encounter drastically increasing performance and flexibility requirements. In this paper, we present a novel flexible multiprocessor platform for high throughput turbo decoding. The proposed platform enables exploiting all parallelism levels of turbo decoding applications to fulfill performance requirements. In order to fulfill flexibility requirements, the platform is structured around configurable application-specific instruction-set processors (ASIP) combined with an efficient memory and communication interconnect scheme. The designed ASIP has an single instruction multiple data (SIMD) architecture with a specialized and extensible instruction-set and 6-stages pipeline control. The attached memories and communication interfaces enable its integration in multiprocessor architectures. These multiprocessor architectures benefit from the recent shuffled decoding technique introduced in the turbo-decoding field to achieve higher throughput. The major characteristics of the proposed platform are its flexibility and scalability which make it reusable for all simple and double binary turbo codes of existing and emerging standards. Results obtained for double binary WiMAX turbo codes demonstrate around 250 Mb/s throughput using 16-ASIP multiprocessor architecture.