A Linear Systolic Array for Real-Time Morphological Image Processing
Journal of VLSI Signal Processing Systems
Reconfigurable pipelined 2-D convolvers for fast digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level abstraction semantics
Proceedings of the 15th international symposium on System Synthesis
ASIP Design Methodologies: Survey and Issues
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Input data reuse in compiling window operations onto reconfigurable hardware
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Optimized Generation of Data-Path from C Codes for FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ASIP approach for implementation of H.264/AVC
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
IEEE Annals of the History of Computing
Optimizing synchronous systems
SFCS '81 Proceedings of the 22nd Annual Symposium on Foundations of Computer Science
Design of an application-specific instruction set processor for high-throughput and scalable FFT
Proceedings of the Conference on Design, Automation and Test in Europe
Enhancing the performance of symmetric-key cryptography via instruction set extensions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
From parallelism levels to a multi-ASIP architecture for turbo decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive scan rate up-conversion system based on human visual characteristics
IEEE Transactions on Consumer Electronics
Motion adaptive interpolation with horizontal motion detection for deinterlacing
IEEE Transactions on Consumer Electronics
Fuzzy logic-based embedded system for video de-interlacing
Applied Soft Computing
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This paper presents a systematic approach to the design of application-specific instruction-set processors for high speed computation of local neighborhood functions and intra-field deinterlacing. The intended application is real-time processing of high definition video. The approach aims at an efficient utilization of the available memory bandwidth by fully exploiting the data parallelism inherent to the target algorithm class. An appropriate choice of custom instructions and application-specific registers is used together with a very long instruction word architecture in order to mimic a pipelined systolic array. This leads to a processing speed close to the limit imposed by memory bandwidth constraints. For three intra-field deinterlacing algorithms and 2-D convolution with four kernel sizes, the design approach yields speedup factors between 36 and 1330, Area-Time (AT) product improvements between 12× and 243×, and energy consumption reduction factors between 13 and 262.