A Linear Systolic Array for Real-Time Morphological Image Processing

• Authors: K. I. Diamantaras;S. Y. Kung
• Venue: Journal of VLSI Signal Processing Systems
• Year: 1997

Mathematical morphology has proven to be a very useful tool forapplications such as smoothing, image skeletonization, patternrecognition, machine vision, etc. In this paper we present a1-dimensional systolic architecture for the basic gray-scalemorphology operations: dilation and erosion. Most other morphologicaloperations like opening and closing, are also supported by thearchitecture since these operations are combinations of the basicones. The advantages of our design stem from the fact that it haspipeline period α = 1 (i.e., 100% processorutilization), it requires simple communications, and it is exploitingthe simplicity of the morphological operations to make it possible toimplement them in a linear target machine although the startingalgorithm is a generalized 2-D convolution. We also propose a LocallyParallel Globally Sequential (LPGS) partitioning strategy for thebest mapping of the algorithm onto the architecture. We conclude thatfor this particular problem LPGS is better than LSGP in a practicalsense (pinout, memory requirement, etc.). Furthermore, we propose achip design for the basic component of the array that will allowreal-time video processing for 8- and 16-bit gray-level frames ofsize 512 × 512, using only 32 processors inparallel. The design is easily scalable so it can be custom-tayloredto fit the requirement of each particular application.