Fast Implementation of Binary Morphological Operations on Hardware-Efficient Systolic Architectures

  • Authors:

  • E. N. Malamas;A. G. Malamos;T. A. Varvarigou

  • Affiliations:

  • Electronics Laboratory, Department of Electronics and Computer Engineering, Technical University of Crete, Gr-731 00 Chania, Greece;Electronics Laboratory, Department of Electronics and Computer Engineering, Technical University of Crete, Gr-731 00 Chania, Greece;Telecomunications Laboratory, Department of Electrical and Computer Engineering, National Technical University of Athens, Eroon Polutechniou 9, GR-157 73 Zografou, Athens, Greece

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2000

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Abstract

In this paper we present novel systolic architectures for the fast execution of common morphological operations, that is dilation, erosion, closing, and opening. Their novelty stems from the fact that the same unit, the combined Erosion-Dilation Architecture (EDA), is used to perform either dilation, or erosion, or both of them in parallel (depending on control signals). The proposed architectures show a major advantage on using reduced resources for storing the structuring element (SE), lead to full resource utilization, and provide high processing rates. We concentrate on 1-dim structuring elements and present an improved architecture, that performs dilation and erosion in half the time compared to other architectures, using a workload partitioning technique. Furthermore, the amenability of the EDA to VLSI implementation is exemplified by a processor that performs binary morphological operations with 1 × 3 structuring sets. Finally, we show that the modularity of the proposed architectures allows the direct extension to 2-dim morphology.