Watersheds in Digital Spaces: An Efficient Algorithm Based on Immersion Simulations
IEEE Transactions on Pattern Analysis and Machine Intelligence
A Linear Systolic Array for Real-Time Morphological Image Processing
Journal of VLSI Signal Processing Systems
Signal Processing - Video segmentation for content-based processing manipulation
Fast Implementation of Binary Morphological Operations on Hardware-Efficient Systolic Architectures
Journal of VLSI Signal Processing Systems
Computer and Robot Vision
Image Analysis and Mathematical Morphology
Image Analysis and Mathematical Morphology
The MPEG-4 video standard verification model
IEEE Transactions on Circuits and Systems for Video Technology
Automatic segmentation of moving objects for video object plane generation
IEEE Transactions on Circuits and Systems for Video Technology
Unsupervised video segmentation based on watersheds and temporal tracking
IEEE Transactions on Circuits and Systems for Video Technology
Video segmentation for content-based coding
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the MPEG-7 standard
IEEE Transactions on Circuits and Systems for Video Technology
Efficient moving object segmentation algorithm using background registration technique
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
Real-time shape description system based on MPEG-7 descriptors
Journal of Systems Architecture: the EUROMICRO Journal
Efficient content analysis engine for visual surveillance network
IEEE Transactions on Circuits and Systems for Video Technology
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Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 驴m 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems.