Decomposition of Convex Polygonal Morphological Structuring Elements into Neighborhood Subsets
IEEE Transactions on Pattern Analysis and Machine Intelligence
A fast algorithm for local minimum and maximum filters on rectangular and octagonal kernels
Pattern Recognition Letters
Recursive Implementation of Erosions and Dilations Along Discrete Lines at Arbitrary Angles
IEEE Transactions on Pattern Analysis and Machine Intelligence
A Linear Systolic Array for Real-Time Morphological Image Processing
Journal of VLSI Signal Processing Systems
Efficient Dilation, Erosion, Opening, and Closing Algorithms
IEEE Transactions on Pattern Analysis and Machine Intelligence
Digital Lines and Digital Convexity
Digital and Image Geometry, Advanced Lectures [based on a winter school held at Dagstuhl Castle, Germany in December 2000]
Image Analysis and Mathematical Morphology
Image Analysis and Mathematical Morphology
An Efficient Hardware Architecture without Line Memories for Morphological Image Processing
ACIVS '08 Proceedings of the 10th International Conference on Advanced Concepts for Intelligent Vision Systems
Fast computation of a class of running filters
IEEE Transactions on Signal Processing
Recursive erosion, dilation, opening, and closing transforms
IEEE Transactions on Image Processing
IEEE Transactions on Circuits and Systems for Video Technology
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This paper presents a new algorithm for efficient computation of morphological operations for gray images and the specific hardware. The method is based on a new recursive morphological decomposition method of 8-convex structuring elements by only causal two-pixel structuring elements (2PSE). Whatever the element size, erosion or/and dilation can then be performed during a unique raster-like image scan involving a fixed reduced analysis neighborhood. The resulting process offers low computation complexity combined with easy description of the element form. The dedicated hardware is generic and fully regular, built from elementary interconnected stages. It has been synthesized into an FPGA and achieves high-frequency performances for any shape and size of structuring element.