VLSI architectures for SISO-APP decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Scalable System Architecture for High-Throughput Turbo-Decoders
Journal of VLSI Signal Processing Systems
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
From parallelism levels to a multi-ASIP architecture for turbo decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mapping interleaving laws to parallel turbo and LDPC decoder architectures
IEEE Transactions on Information Theory
On maximum contention-free interleavers and permutation polynomials over integer rings
IEEE Transactions on Information Theory
On chip interconnects for multiprocessor turbo decoding architectures
Microprocessors & Microsystems
Design and implementation of turbo decoder for TETRA release 2 - TEDS
ICHIT'11 Proceedings of the 5th international conference on Convergence and hybrid information technology
A low-complexity turbo decoder architecture for energy-efficient wireless sensor networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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3GPP long term evolution (LTE) enhances the wireless communication standards UMTS and HSDPA towards higher throughput. A throughput of 150 Mbit/s is specified for LTE using 2x2 MIMO. For this, highly punctured Turbo codes with rates up to 0.95 are used for channel coding, which is a big challenge for decoder design. This paper investigates efficient decoder architectures for highly punctured LTE Turbo codes. We present a 150 Mbit/s 3GPP LTE Turbo code decoder, which is part of an industrial SDR multi-standard baseband processor chip.