Wireless integrated network sensors
Communications of the ACM
Memory optimization of MAP turbo decoder algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wireless sensor networks: a survey
Computer Networks: The International Journal of Computer and Telecommunications Networking
Architectural strategies for low-power VLSI turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI Architectural design tradeoffs for sliding-window Log-MAP decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Error control coding in low-power wireless sensor networks: when is ECC energy-efficient?
EURASIP Journal on Wireless Communications and Networking
High-speed recursion architectures for MAP-based turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Unified convolutional/turbo decoder design using tile-based timing analysis of VA/MAP kernel
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An energy-efficient error correction scheme for IEEE 802.15.4 wireless sensor networks
IEEE Transactions on Circuits and Systems II: Express Briefs
A 150Mbit/s 3GPP LTE turbo code decoder
Proceedings of the Conference on Design, Automation and Test in Europe
Highly-parallel decoding architectures for convolutional turbo codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Turbo Coding, Turbo Equalisation and Space-Time Coding: EXIT-Chart-Aided Near-Capacity Designs for Wireless Channels
IEEE Journal on Selected Areas in Communications
Design of a transport triggered vector processor for turbo decoding
Analog Integrated Circuits and Signal Processing
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Turbo codes have recently been considered for energy-constrained wireless communication applications, since they facilitate a low transmission energy consumption. However, in order to reduce the overall energy consumption, lookup table-log-BCJR (LUT-Log-BCJR) architectures having a low processing energy consumption are required. In this paper, we decompose the LUT-Log-BCJR architecture into its most fundamental add compare select (ACS) operations and perform them using a novel low-complexity ACS unit. We demonstrate that our architecture employs an order of magnitude fewer gates than the most recent LUT-Log-BCJR architectures, facilitating a 71% energy consumption reduction. Compared to state-of-the-art maximum logarithmic Bahl-Cocke-Jelinek-Raviv implementations, our approach facilitates a 10% reduction in the overall energy consumption at ranges above 58 m.