A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Scalable and Area Efficient Concurrent Interleaver for High Throughput Turbo-Decoders
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
SODA: A Low-power Architecture For Software Radio
Proceedings of the 33rd annual international symposium on Computer Architecture
Design to Minimize Diameter on Building-Block Network
IEEE Transactions on Computers
A Design for Directed Graphs with Minimum Diameter
IEEE Transactions on Computers
de Bruijn graph as a low latency scalable architecture for energy efficient massive NoCs
Proceedings of the conference on Design, automation and test in Europe
Dynamic reconfiguration approach for high speed turbo decoding using circular rings
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Reliable network-on-chip based on generalized de Bruijn graph
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
On optimal and near-optimal turbo decoding using generalized max* operator
IEEE Communications Letters
Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
A 150Mbit/s 3GPP LTE turbo code decoder
Proceedings of the Conference on Design, Automation and Test in Europe
Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Optimal decoding of linear codes for minimizing symbol error rate (Corresp.)
IEEE Transactions on Information Theory
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Journal on Selected Areas in Communications
A network-on-chip-based turbo/LDPC decoder architecture
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Turbo codes are among the most powerful and widely adopted error correcting codes in several communication applications. The high throughput requirements of current and future standards impose that parallel decoders composed by multiple interconnected processing elements are used at the receiver side to efficiently decode turbo codes. In this work, on chip interconnects for multiprocessor turbo decoding are investigated. Due to the dominant trend towards the design of flexible, multi-standard decoders, capable to support the decoding of several turbo codes, the Network-on-Chip approach is seen as a viable and promising solution, although the specific characteristics of the addressed application impose a drastic simplification in the network organization. Both indirect and direct network topologies are studied and experimental results show that a Network-on-Chip based decoder made of 16 processing elements can achieve a throughput of several hundreds of Mbps. Moreover, the area required by the network compares favorably with previously published works on flexible interconnect architectures for turbo decoding and the cost overhead of NOC based solutions with respect to a fully dedicated implementation is limited to 13%.