Interleavers for turbo codes using permutation polynomials over integer rings
IEEE Transactions on Information Theory
On maximum contention-free interleavers and permutation polynomials over integer rings
IEEE Transactions on Information Theory
IEEE Journal on Selected Areas in Communications
Reconfigurable turbo decoder with parallel architecture for 3GPP LTE system
IEEE Transactions on Circuits and Systems II: Express Briefs
On chip interconnects for multiprocessor turbo decoding architectures
Microprocessors & Microsystems
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A static and dynamic reconfiguration method and apparatus that can be utilized for parallel turbo decoding is described. The methodology is based on the property of a class of polynomials that can provide contention free permutation. A new ring interconnect methodology is presented that can be used for quadratic permutation polynomial (QPP) based interleaved memory access. An efficient interleave-deinterleave mechanism using QPP interleaver is also presented for a new power driven reconfigurable solution. It consists of multiple SISO modules connected by a mix of dynamic and static reconfigurable interconnect with an efficient memory segmentation that matches the underlying reconfigurable fabric. The parallel blocks are controlled by a unified state machine mapped external to the reconfigurable fabric. The overall array is implemented on 90nm Toshiba standard cell library occupying an area of 11.11 mm2 with reconfigurable speeds of 7.8-131.28 Mb/sec and the corresponding power consumption of 53-762 mW.