Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder
Proceedings of the 45th annual Design Automation Conference
de Bruijn graph as a low latency scalable architecture for energy efficient massive NoCs
Proceedings of the conference on Design, automation and test in Europe
Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
On chip interconnects for multiprocessor turbo decoding architectures
Microprocessors & Microsystems
A novel 3D NoC architecture based on De Bruijn graph
Computers and Electrical Engineering
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In this paper, we propose the generalized de Bruijn graph as a reliable and efficient network topology for a Network on-Chip (NoC) design. We also propose a reliable routing algorithm to detour a problematic (i.e., faulty or congested) link. Our experimental results show that the latency and energy consumption of generalized de Bruijn graph are much less with compared to Mesh and Torus, the two common NoC architectures in the literature. The low energy consumption of de Bruijn graph-based NoC makes it suitable for portable devices which have to operate on limited batteries. Also, the gate level implementation of the proposed reliable routing shows a small area, power, and timing overheads due to the proposed reliable routing algorithm.