A novel 3D NoC architecture based on De Bruijn graph

Authors:
Yiou Chen;Jianhao Hu;Xiang Ling;Tingting Huang
Affiliations:
National Key Lab of Science and Technology on Communications, University of Electronic Science and Technology of China, Chengdu 610054, China;National Key Lab of Science and Technology on Communications, University of Electronic Science and Technology of China, Chengdu 610054, China;National Key Lab of Science and Technology on Communications, University of Electronic Science and Technology of China, Chengdu 610054, China;National Key Lab of Science and Technology on Communications, University of Electronic Science and Technology of China, Chengdu 610054, China
Venue:
Computers and Electrical Engineering
Year:
2012

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Abstract

Networks on Chip (NoC) and 3-Dimensional Integrated Circuits (3D IC) have been proposed as the solutions to the ever-growing communication problem in System on Chip (SoC). Most of contemporary 3D architectures are based on Mesh topology, which fails to achieve small latency and power consumption due to its inherent large network diameter. Moreover, the conventional XY routing lacks the ability of fault tolerance. In this paper, we propose a new 3D NoC architecture, which adopts De Bruijn graph as the topology in physical horizontal planes by leveraging its advantage of small latency, simple routing, low power, and great scalability. We employ an enhanced pillar structure for vertical interconnection. We design two shifting based routing algorithms to meet separate performance requirements in latency and computing complexity. Also, we use fault tolerant routing to guarantee reliable data transmission. Our simulation results show that the proposed 3D NoC architecture achieves better network performance and power efficiency than 3D Mesh and XNoTs topologies.