Microstructure examination of copper wafer bonding
Journal of Electronic Materials - Special issue on advances in materials science of IC interconnects and packaging
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
Developing mesochronous synchronizers to enable 3D NoCs
Proceedings of the conference on Design, automation and test in Europe
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
Proceedings of the 2nd international conference on Nano-Networks
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
From 2D to 3D NoCs: a case study on worst-case communication performance
Proceedings of the 2009 International Conference on Computer-Aided Design
An error tolerance scheme for 3D CMOS imagers
Proceedings of the 47th Design Automation Conference
ACM SIGDA Newsletter
TSV redundancy: architecture and design issues in 3D IC
Proceedings of the Conference on Design, Automation and Test in Europe
Sunfloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Vertical interconnects squeezing in symmetric 3D mesh network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Assembling 2D blocks into 3D chips
Proceedings of the 2011 international symposium on Physical design
3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
Fault-tolerant 3D clock network
Proceedings of the 48th Design Automation Conference
Adaptive inter-layer message routing in 3D networks-on-chip
Microprocessors & Microsystems
A novel graceful degradable routing algorithm for 3D on-chip networks
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems
Journal of Electronic Testing: Theory and Applications
Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods
Journal of Electronic Testing: Theory and Applications
A novel 3D NoC architecture based on De Bruijn graph
Computers and Electrical Engineering
Small delay testing for TSVs in 3-D ICs
Proceedings of the 49th Annual Design Automation Conference
Combined heuristics for synthesis of SOCs with time and power constraints
Computers and Electrical Engineering
An enhanced double-TSV scheme for defect tolerance in 3D-IC
Proceedings of the Conference on Design, Automation and Test in Europe
On effective and efficient in-field TSV repair for stacked 3D ICs
Proceedings of the 50th Annual Design Automation Conference
TSV redundancy: architecture and design issues in 3-D IC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
In-situ method for TSV delay testing and characterization using input sensitivity analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-cost error tolerance scheme for 3-D CMOS imagers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On effective TSV repair for 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees
Proceedings of the International Conference on Computer-Aided Design
Virtualized and fault-tolerant inter-layer-links for 3D-ICs
Microprocessors & Microsystems
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
Journal of Parallel and Distributed Computing
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Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Vias (TSVs) provide a promising area- and power-efficient way to support communication between different stack layers. Unfortunately, low TSV yield significantly impacts design of three-dimensional die stacks with a large number of TSVs. This paper presents a defecttolerance technique for TSVs-based multi-bit links through an efficient and effective use of redundancy. This technique is ideally suited for three-dimensional network-on-chip (NoC) links. Simulation results demonstrate significant yield improvement, from 66% to 98%, with a low area cost (17% on a vertical link in a NoC switch, which leads a modest 2.1% increase the total switch area) in 130nm technology, with minimal impact of VLSI design and test flows.