Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Developing mesochronous synchronizers to enable 3D NoCs
Proceedings of the conference on Design, automation and test in Europe
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
More than Moore: Creating High Value Micro/Nanoelectronics Systems
More than Moore: Creating High Value Micro/Nanoelectronics Systems
SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips
Proceedings of the Conference on Design, Automation and Test in Europe
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While lithographic advances have made it possible to manufacture chips with ever smaller features (Moore's Law), the cost of the required machinery has been steadily increasing, and speculation is that finer geometries will become, if not technically infeasible, impractically expensive. At the same time, the "More than Moore" paradigm [1] has been advocating the creation of chip value through the integration of functionality beyond standard digital CMOS, for example sensing, radiofrequency, optoelectronics. These two trends meet in "3D" chip integration, whereby multiple dies, independently manufactured in possibly very heterogeneous technologies, are stacked together to provide a large amount of functionality in a small package footprint.