Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A hierarchical modeling framework for on-chip communication architectures
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Topology optimization for application-specific networks-on-chip
Proceedings of the 2004 international workshop on System level interconnect prediction
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
Physical Design for 3D System on Package
IEEE Design & Test
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
Performance Evaluation for Three-Dimensional Networks-On-Chip
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
Proceedings of the 2nd international conference on Nano-Networks
Synthesis of networks on chips for 3D systems on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An outlook on design technologies for future integrated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Circuits and Systems II: Express Briefs
Networks on Chips: from research to products
Proceedings of the 47th Design Automation Conference
ACM SIGDA Newsletter
Design of networks on chips for 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Application-specific 3D Network-on-Chip design using simulated allocation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
B2RAC: a physical express link addition methodology for network on chip
Proceedings of the 4th International Workshop on Network on Chip Architectures
Chemical-mechanical polishing aware application-specific 3D NoC design
Proceedings of the International Conference on Computer-Aided Design
Optimized 3D Network-on-Chip Design Using Simulated Allocation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A buffer-sizing algorithm for network-on-chips with multiple voltage-frequency Islands
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Combined heuristics for synthesis of SOCs with time and power constraints
Computers and Electrical Engineering
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Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on Chip (NoC) interconnect for a 3D SoC that not only meets the application performance constraints, but also the constraints imposed by the 3D technology, is a significant challenge. In this work we present a design tool, SunFloor 3D, to synthesize application-specific 3D NoCs. The proposed tool determines the best NoC topology for the application, finds paths for the communication flows, assigns the network components on to the 3D layers and performs a placement of them in each layer. We perform experiments on several SoC benchmarks and present a comparative study between 3D and 2D NoC designs. Our studies show large improvements in interconnect power consumption (average of 38%) and delay (average of 13%) for the 3D NoC when compared to the corresponding 2D implementation. Our studies also show that the synthesized topologies result in large power (average of 54%) and delay savings (average of 21%) when compared to standard topologies.