B2RAC: a physical express link addition methodology for network on chip

Authors:
Jiajia Jiao;Yuzhuo Fu
Affiliations:
Shanghai Jiao Tong University, China;Shanghai Jiao Tong University, China
Venue:
Proceedings of the 4th International Workshop on Network on Chip Architectures
Year:
2011

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Abstract

As a compromise solution for Network on Chip (NoC) architecture design, adding some application-specified express links based on regular topology such as Mesh has been proved to exploit the benefits offered by both complete regularity and partial topology customization. Following this perspective, an enhanced link addition methodology B2RAC is proposed to automatically synthesize new NoC architecture for guiding effective design in this paper, including: i) flexible branch bound (B2) algorithm for best link set selection iteratively; ii) efficient routing-aware (RA) performance estimation model for each link addition procedure; iii) configurable(C) switches with fifos for the additional long link equivalence. The simulation results show the optimized architecture of B2RAC methodology can bring better performance (latency decreases by 16.5% and 23.46% for typical applications VOPD and MWD respectively) with good flexibility for real application traffic over up-to-date link addition policy.