Multilevel algorithms for multi-constraint graph partitioning
SC '98 Proceedings of the 1998 ACM/IEEE conference on Supercomputing
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
NoCs: A new Contract between Hardware and Software
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Topology optimization for application-specific networks-on-chip
Proceedings of the 2004 international workshop on System level interconnect prediction
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
An Improved Min-Cut Algonthm for Partitioning VLSI Networks
IEEE Transactions on Computers
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
B2RAC: a physical express link addition methodology for network on chip
Proceedings of the 4th International Workshop on Network on Chip Architectures
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
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One of the most challenging problems in Application-Specific Networks-on-Chip (ASNoC) design is to customize the topological structure of the on-chip network in order to meet the application requirements with the minimum possible cost. In this paper, the area cost of ASNoCs is reduced by using network partitioning techniques. The enhancement in area cost is achieved by reducing both routers area and the number of global links. Given the application core graph, Fiduccia-Mattheyses (FM) algorithm is adopted with modification to formulate the partitioning problem as an optimization one. As a proof of concept, our technique is applied to three different applications with different number of cores. Results show that the proposed technique is a promising way to reduce the ASNoC area compared to other topology generation techniques.