Chemical-mechanical polishing aware application-specific 3D NoC design

Authors:
Wooyoung Jang;Ou He;Jae-Seok Yang;David Z. Pan
Affiliations:
SoC Platform Development Team, Samsung Electronics, Yongin-City, South Korea;IBM System & Technology Group, Beijing, China;CAE Team, Samsung Electronics, Hwaseung-City, South Korea;The University of Texas at Austin, Austin
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2011

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Abstract

In this paper, we propose the first chemical-mechanical polishing (CMP) aware application-specific three-dimensional (3D) network-on-chip (NoC) design that minimizes through-silicon-via (TSV) height variation, thus reduces its bonding failure, and meanwhile optimizes conventional NoC design objectives. Our 3D NoC design assigns cores to proper silicon layers, determines the 3D NoC topology, allocates routing paths, and then floorplans cores, routers and TSV arrays by a CMP-aware manner. The key idea behind this 3D NoC design flow is to determine the CMP-aware 3D NoC topology where TSV arrays with low and uniform metal density are inserted between adjacent layers. Experimental results show that our CMP-aware 3D NoC design can achieves lower TSV height variation, higher performance and lower power consumption than the previous state-of-the-art 3D NoC designs.