Design of networks on chips for 3D ICs

Authors:
Srinivasan Murali;Luca Benini;Giovanni De Micheli
Affiliations:
iNoCs, Lausanne, Switzerland and LSI, EPFL, Lausanne, Switzerland;University of Bologna, Bologna, Italy;LSI, EPFL, Lausanne, Switzerland
Venue:
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Year:
2010

Citing 3
Cited 0

A generic architecture for on-chip packet-switched interconnections

DATE '00 Proceedings of the conference on Design, automation and test in Europe
On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect
SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips

Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

Three-dimensional integrated circuits, where multiple silicon layers are stacked vertically have emerged recently. The 3D ICs have smaller form factor, shorter and efficient use of wires and allow integration of diverse technologies in the same device. The use of Networks on Chips (NoCs) to connect components in a 3D chip is a necessity. In this short paper, we present an outline on designing application-specific NoCs for 3D ICs.