High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Planar-adaptive routing: low-cost adaptive networks for multiprocessors
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Queuing delays for uniform and nonuniform traffic patterns in a MIN
ACM SIGSIM Simulation Digest
Planar-adaptive routing: low-cost adaptive networks for multiprocessors
Journal of the ACM (JACM)
A Theory of Fault-Tolerant Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Fault-Tolerant Wormhole Routing Algorithms for Mesh Networks
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
The Reliable Router: A Reliable and High-Performance Communication Substrate for Parallel Computers
PCRCW '94 Proceedings of the First International Workshop on Parallel Computer Routing and Communication
A large scale, homogeneous, fully distributed parallel machine, I
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Adaptive Box-Based Efficient Fault-tolerant Routing in 3D Torus
ICPADS '05 Proceedings of the 11th International Conference on Parallel and Distributed Systems - Volume 01
Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Performance Evaluation for Three-Dimensional Networks-On-Chip
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip
Proceedings of the 45th annual Design Automation Conference
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Practical Deadlock-Free Fault-Tolerant Routing in Meshes Based on the Planar Network Fault Model
IEEE Transactions on Computers
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
Real-Time Systems and Programming Languages: Ada, Real-Time Java and C/Real-Time POSIX
Real-Time Systems and Programming Languages: Ada, Real-Time Java and C/Real-Time POSIX
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures
Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures
Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC
BWCCA '10 Proceedings of the 2010 International Conference on Broadband, Wireless Computing, Communication and Applications
Advanced Design Issues for OASIS Network-on-Chip Architecture
BWCCA '10 Proceedings of the 2010 International Conference on Broadband, Wireless Computing, Communication and Applications
A resilient on-chip router design through data path salvaging
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MCSOC '12 Proceedings of the 2012 IEEE 6th International Symposium on Embedded Multicore SoCs
MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip
DSD '12 Proceedings of the 2012 15th Euromicro Conference on Digital System Design
Low-overhead Routing Algorithm for 3D Network-on-Chip
ICNC '12 Proceedings of the 2012 Third International Conference on Networking and Computing
Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategy
Proceedings of the Conference on Design, Automation and Test in Europe
AFRA: a low cost high performance reliable routing for 3D mesh NoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Deadlock-Recovery Support for Fault-tolerant Routing Algorithms in 3D-NoC Architectures
MCSOC '13 Proceedings of the 2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip
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Three-Dimensional Networks-on-Chip (3D-NoC) has been presented as an auspicious solution merging the high parallelism of Network-on-Chip (NoC) interconnect paradigm with the high-performance and lower interconnect-power of 3-dimensional integration circuits. However, 3D-NoC systems are exposed to a variety of manufacturing and design factors making them vulnerable to different faults that cause corrupted message transfer or even catastrophic system failures. Therefore, a 3D-NoC system should be fault-tolerant to transient malfunctions or permanent physical damages. In this paper, we present an efficient fault-tolerant routing algorithm, called Hybrid-Look-Ahead-Fault-Tolerant (HLAFT), which takes advantage of both local and look-ahead routing to boost the performance of 3D-NoC systems while ensuring fault-tolerance. A deadlock-recovery technique associated with HLAFT, named Random-Access-Buffer (RAB), is also presented. RAB takes advantage of look-ahead routing to detect and remove deadlock with no considerably additional hardware complexity. We implemented the proposed algorithm and deadlock-recovery technique on a real 3D-NoC architecture (3D-OASIS-NoC) and prototyped it on FPGA. Evaluation results show that the proposed algorithm performs better than XYZ, even when considering high fault-rates (i.e., = 20%), and outperforms our previously designed Look-Ahead-Fault-Tolerant routing (LAFT) demonstrated in latency/flit reduction that can reach 12.5% and a throughput enhancement reaching 11.8% in addition to 7.2% dynamic-power saving thanks to the Power-management module integrated with HLAFT.