Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
Journal of Parallel and Distributed Computing
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Despite the higher scalability and parallelism integration offered by Network-on-Chip (NoC) over the traditional shared-bus based systems, it is still not an ideal solution for future large scale Systems-on-Chip (SoCs), due to some limitations such as high power consumption and high cost communication. Recently, extending 2D-NoC to the third dimension (3D-NoC) has been proposed to deal with these problems. One of the most important design choices for 3D-NoC designs is the implementation of a fast and high throughput system with a reasonable hardware complexity. Moreover, adopting an efficient routing algorithm has become an important task since the flits' path selection has a direct impact on the overall system performance. In this paper, we propose a low overhead, and high throughput 3D-NoC routing algorithm named Look-ahead-XYZ (LA-XYZ). We implemented the proposed algorithm in our 3D-NoC deign, named 3D-OASIS-NoC, and we prototyped it on FPGA. We evaluated its performance using Transpose traffic pattern and two selected real applications (JPEG-encoder and Matrix-multiplication). Evaluation results show that the proposed algorithm reduces the communication latency by 29.22% and 35.12% and enhances the throughput with an average of 26% and 38.95% when compared to XYZ and Randomized Partially Minimal (RPM) routing algorithms respectively.