Planar-adaptive routing: low-cost adaptive networks for multiprocessors
Journal of the ACM (JACM)
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
A simple fault-tolerant adaptive and minimal routing approach in 3-D meshes
Journal of Computer Science and Technology
Fault-Tolerant Routing in Meshes/Tori Using Planarly Constructed Fault Blocks
ICPP '05 Proceedings of the 2005 International Conference on Parallel Processing
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Region-based routing: a mechanism to support efficient routing algorithms in NoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-cost router microarchitecture for on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
TSV redundancy: architecture and design issues in 3D IC
Proceedings of the Conference on Design, Automation and Test in Europe
A highly resilient routing algorithm for fault-tolerant NoCs
Proceedings of the Conference on Design, Automation and Test in Europe
RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip
IOLTS '10 Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Fault-Tolerant Vertical Link Design for Effective 3D Stacking
IEEE Computer Architecture Letters
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategy
Proceedings of the Conference on Design, Automation and Test in Europe
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
Journal of Parallel and Distributed Computing
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Three-dimensional network-on-chips are suitable communication fabrics for high-density 3D many-core ICs. Such networks have shorter communication hop count, compared to 2D NoCs, and enjoy fast and power efficient TSV wires in vertical links. Unfortunately, the fabrication process of TSV connections has not matured yet, which results in poor vertical links yield. In this work, we address this challenge and introduce AFRA, a deadlock-free routing algorithm for 3D mesh-based NoCs that tolerates faults on vertical links. AFRA is designed to be simple, high performance, and robust. The simplicity is achieved by applying ZXY and XZXY routings in the absence and presence of fault, respectively. Furthermore, AFRA, as will be proved, is deadlock-free when all vertical faulty links have the same direction. This enables the routing to save virtual channels for performance rather than scarifying them for deadlock avoidance. Finally, AFRA provides robustness, which means supporting connection for all possible pairs of communicating nodes in high fault rates. AFRA is evaluated, though cycle accurate network simulation, and is compared with planar adaptive routing. Results reveal that AFRA significantly outperforms planar adaptive routing in both synthetic and real traffic patterns. In addition, the robustness of AFRA is calculated analytically.