Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
3D Integration: Technology and Applications
3D Integration: Technology and Applications
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A 3D prototyping chip based on a wafer-level stacking technology
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Test Challenges for 3D Integrated Circuits
IEEE Design & Test
Assembling 2D blocks into 3D chips
Proceedings of the 2011 international symposium on Physical design
Robust signaling techniques for through silicon via bundles
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Fault-tolerant 3D clock network
Proceedings of the 48th Design Automation Conference
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems
Journal of Electronic Testing: Theory and Applications
TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation
Proceedings of the 49th Annual Design Automation Conference
Multiobjective optimization of deadspace, a critical resource for 3D-IC integration
Proceedings of the International Conference on Computer-Aided Design
An enhanced double-TSV scheme for defect tolerance in 3D-IC
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
On effective and efficient in-field TSV repair for stacked 3D ICs
Proceedings of the 50th Annual Design Automation Conference
AFRA: a low cost high performance reliable routing for 3D mesh NoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
On effective TSV repair for 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Systems Architecture: the EUROMICRO Journal
Optimal placement of vertical connections in 3D Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
Virtualized and fault-tolerant inter-layer-links for 3D-ICs
Microprocessors & Microsystems
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs
Integration, the VLSI Journal
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3D technology provides many benefits including high density, high band-with, low-power, and small form-factor. Through Silicon Via (TSV), which provides communication links for dies in vertical direction, is a critical design issue in 3D integration. Just like other components, the fabrication and bonding of TSVs can fail. A failed TSV may cause a number of known-good-dies that are stacked together to be discarded. This can severely increase the cost and decrease the yield as the number of dies to be stacked increases. A redundant TSV architecture with reasonable cost for ASICs is proposed in this paper. Design issues including recovery rate and timing problem are addressed. Based on probabilistic models, some interesting findings are reported. First, the probability that three or more TSVs are failed in a tier is less than 0.002%. Assumption of that there are at most two failed TSVs in a tier is sufficient to cover 99.998% of all possible faulty free and faulty cases. Next, with one redundant TSV allocated to one TSV block, limiting the number of TSVs in each TSV block to be no greater than 50 and 25 leads to 90% and 95% recovery rates when 2 failed TSVs are assumed. Finally, analysis on overall yield shows that the proposed design can successfully recover most of the failed chips and increase the yield of TSV bonding to 99.99%. This can effectively reduce the cost of manufacturing 3D ICs.