The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Proceedings of the 6th international workshop on Hardware/software codesign
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
Thermal via planning for 3-D ICs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A 3D prototyping chip based on a wafer-level stacking technology
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
TSV redundancy: architecture and design issues in 3D IC
Proceedings of the Conference on Design, Automation and Test in Europe
PinComm: Characterizing Intra-application Communication for the Many-Core Era
ICPADS '10 Proceedings of the 2010 IEEE 16th International Conference on Parallel and Distributed Systems
Vertical interconnects squeezing in symmetric 3D mesh network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Benchmarking modern multiprocessors
Benchmarking modern multiprocessors
A Layer-Multiplexed 3D On-Chip Network Architecture
IEEE Embedded Systems Letters
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3-Dimensional Networks-on-Chip (3D NoC) have emerged as the promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoCs) interconnect. Due to the cost in terms of thermal, yield, chip area and design complexity, minimizing the number of Through-Silicon-Via (TSVs) in 3D ICs has become on the most important design issues. In this paper, we will present several stable, simple and deadlock-free generic routing algorithms for 3D NoCs with different reduced vertical link density topologies, which can maintain the 3D NoCs performance and save the system cost (TSV number, chip area, system power, etc.). The experimental results have been extracted from our cycle-accurate GSNOC simulator and have shown that our routing algorithms can maintain the system performance up to reducing 50% of TSVs number in comparison to the 100% TSVs number with ZXY routing algorithm configuration.