A 3D prototyping chip based on a wafer-level stacking technology

Authors:
Nobuaki Miyakawa
Affiliations:
Honda Research Institute Japan Co., Ltd.
Venue:
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Year:
2009

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Abstract

We have developed a new 3-dimensional stacking technology using wafer-to-wafer stacked method and evaluated the connectivity between TSV and micro-bump. The prototype 3-layer stacking device has been tried using our technology and the functional yield reached more than 60%. Using 8-inch wafer. We propose one of the design methodologies for a 3D stacked device.