A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A 3D prototyping chip based on a wafer-level stacking technology
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
ATS '09 Proceedings of the 2009 Asian Test Symposium
TSV redundancy: architecture and design issues in 3D IC
Proceedings of the Conference on Design, Automation and Test in Europe
3D integration for energy efficient system design
Proceedings of the 48th Design Automation Conference
On effective TSV repair for 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Die stacking based on Through-Silicon Via (TSV) is considered as an efficient way to reducing power consumption and form factor. In the current stage, the failure rate of TSV is still high, so some type of defect tolerance scheme is required. Meanwhile, the concept of double-via, which is normally used in traditional layer to layer interconnection, can be one of the feasible tolerance schemes. Double-via/TSV has a benefit compared to TSV repair: it can eliminate the fuse configuration procedure as well as the fuse layer. However, double-TSV has a problem of signal degradation and leakage caused by short defects. In this work, an enhanced scheme for double-TSV is proposed to solve the short-defect problem through signal path division and VDD isolation. Result shows that the enhanced double-TSV can tolerate both open and short defects, with reasonable area and timing overhead.