A Layer-Multiplexed 3D On-Chip Network Architecture

Authors:
R. Sunkam Ramanujam;B. Lin
Affiliations:
Dept. of Electr. & Comput. Eng., Univ. of California, La Jolla, CA, USA;-
Venue:
IEEE Embedded Systems Letters
Year:
2009

Citing 0
Cited 4

3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans

International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
New heuristic algorithms for low-energy mapping and routing in 3D NoC

International Journal of Computer Applications in Technology
Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies

Journal of Systems Architecture: the EUROMICRO Journal
Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC)

The Journal of Supercomputing

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Abstract

Programmable many-core processors are poised to become a major design option for many embedded applications. In the design of power-efficient embedded many-core processors, the architecture of the on-chip network plays a central role. Many designs have relied on a 2D mesh architecture as the underlying communication fabric. With the emergence of 3D technology, new on-chip network architectures are possible. In this paper, we propose a novel layer-multiplexed (LM) 3D network architecture that takes advantage of the short interlayer wiring delays enabled in 3D technology. In particular, the LM architecture replaces the one-layer-per-hop routing in a conventional 3D mesh with simpler vertical demultiplexing and multiplexing structures. When combined with a layer load-balanced oblivious routing algorithm, it can achieve the same worst-case throughput as the best known oblivious routing algorithm on a conventional 3D mesh. However, in comparison to a conventional 3D mesh, the LM architecture consumes 27% less power, attains 14.5% higher average throughput, and achieves 33% lower worst-case hop count on a 4 times 4 times 4 topology.