The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
TSV redundancy: architecture and design issues in 3D IC
Proceedings of the Conference on Design, Automation and Test in Europe
GA Based Congestion Aware Topology Generation for Application Specific NoC
DELTA '11 Proceedings of the 2011 Sixth IEEE International Symposium on Electronic Design, Test and Application
Benchmarking modern multiprocessors
Benchmarking modern multiprocessors
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The advantages of moving from 2-Dimensional Networks-on-Chip (NoCs) to 3-Dimensional NoCs for any application must be justified by the improvements in performance, power, latency and the overall system costs, especially the cost of Through-Silicon-Via (TSV). The trade-off between the number of TSVs and the 3D NoCs system performance becomes one of the most critical design issues. In this paper, we present a fast and optimized task allocation method for low vertical link density (TSV number) 3D NoCs based many core systems, in comparison to the classic methods as Genetic Algorithm (GA) and Simulated Annealing (SA), our method can save quite a number of design time. We take several state-of-the-art benchmarks and the generic scalable pseudo application (GSPA) with different network scales to simulate the achieved design (by our method), in comparison to GA and SA methods achieved designs, our technique can achieve better performance and lower cost. All the experiments have been done in GSNOC framework (written in SystemC-RTL), which can achieve the cycle accuracy and good flexibility.