Self-test methodology for at-speed test of crosstalk in chip interconnects
Proceedings of the 37th Annual Design Automation Conference
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
IEEE Transactions on Computers
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Is 3D chip technology the next growth engine for performance improvement?
IBM Journal of Research and Development
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
TSV redundancy: architecture and design issues in 3D IC
Proceedings of the Conference on Design, Automation and Test in Europe
Testing TSV-based three-dimensional stacked ICs
Proceedings of the Conference on Design, Automation and Test in Europe
Sunfloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis
LATW '11 Proceedings of the 2011 12th Latin American Test Workshop
Design for test and reliability in ultimate CMOS
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
Three dimensional (3D) integrated systems become a reality nowadays, as Thru-Silicon-Via (TSV) technologies mature. 3D integration promises significant performance and energy efficiency improvements by reducing the signal travel distances and integrating more capabilities on a single chip. High integration costs, thermal management, and poor reliability and yield are major challenges of TSV based 3D chips. High structural and parametric fault rates due to manufacturing defects makes it difficult to achieve high interconnect yield using only spare-based repair solutions. In this paper we address the TSV yield issue by implementing the inter-die links of 3D chips as Configurable fault-tolerant Serial Links (CSLs). When there are not enough available functional TSVs, faults are tolerated by performing data serialization. CSLs help reduce chip costs by improving the TSV yield with very few or no spares at all. For 3D Networks-on-Chip (3D NoCs) we show that the CSL yield improvement comes with moderate area overheads (~12---26%) and small performance penalties (less than 5% average latency overhead).