Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Embedded Memory Test and Repair: Infrastructure IP for SOC Yield
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Dynamic Data-bit Memory Built-In Self- Repair
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Software-based self-test of processors under power constraints
Proceedings of the conference on Design, automation and test in Europe: Proceedings
IBM Journal of Research and Development
Self-Configuration and Reachability Metrics in Massively Defective Multiport Chips
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
NCA '10 Proceedings of the 2010 Ninth IEEE International Symposium on Network Computing and Applications
Systematic software-based self-test for pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor
ETS '11 Proceedings of the 2011 Sixteenth IEEE European Test Symposium
Self-Recovering Parallel Applications in Multi-core Systems
NCA '11 Proceedings of the 2011 IEEE 10th International Symposium on Network Computing and Applications
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems
Journal of Electronic Testing: Theory and Applications
Variability-aware task mapping strategies for many-cores processor chips
IOLTS '11 Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This session brings together specialists from the DfT, DfY and DfR domains that will address key problems together with their solutions for the 14nm node and beyond, dealing with extremely complex chips affected by high defect levels, unpredictable and heterogeneous timing behavior, circuit degradation over time, including extreme situations related with the ultimate CMOS nodes, where all processor nodes, routers and links of single-chip massively parallel tera-device processors could comprise timing faults (such as delay faults or clock skews); a large percentage of these parts are affected by catastrophic failures; all parts experience significant performance degradations over time; and new catastrophic failures occur at low MTBF.