Thinned wafer multi-stack 3DI technology
Microelectronic Engineering
TSV redundancy: architecture and design issues in 3D IC
Proceedings of the Conference on Design, Automation and Test in Europe
An RDL-configurable 3D memory tier to replace on-chip SRAM
Proceedings of the Conference on Design, Automation and Test in Europe
Testing TSV-based three-dimensional stacked ICs
Proceedings of the Conference on Design, Automation and Test in Europe
Is 3D integration an opportunity or just a hype?
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Towards "zero-energy" using NEMFET-based power management for 3D hybrid stacked ICs
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper
Journal of Electronic Testing: Theory and Applications
TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation
Proceedings of the 49th Annual Design Automation Conference
Cu passivation for enhanced low temperature (≤300°C) bonding in 3D integration
Microelectronic Engineering
3D-MMC: a modular 3D multi-core architecture with efficient resource pooling
Proceedings of the Conference on Design, Automation and Test in Europe
Is TSV-based 3D integration suitable for inter-die memory repair?
Proceedings of the Conference on Design, Automation and Test in Europe
TSV redundancy: architecture and design issues in 3-D IC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Challenges and emerging solutions in testing TSV-based 2 1/2D- and 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A hierarchical vision processing architecture oriented to 3D integration of smart camera chips
Journal of Systems Architecture: the EUROMICRO Journal
Microelectronic Engineering
Hi-index | 0.00 |
The first encompassing treatise of this new, but very important field puts the known physical limitations for classic 2D electronics into perspective with the requirements for further electronics developments and market necessities. This two-volume handbook presents 3D solutions to the feature density problem, addressing all important issues, such as wafer processing, die bonding, packaging technology, and thermal aspects.It begins with an introductory part, which defines necessary goals, existing issues and relates 3D integration to the semiconductor roadmap of the industry, before going on to cover processing technology and 3D structure fabrication strategies in detail. This is followed by fields of application and a look at the future of 3D integration.The contributions come from key players in the field, from both academia and industry, including such companies as Lincoln Labs, Fraunhofer, RPI, ASET, IMEC, CEA-LETI, IBM, and Renesas.