Communications of the ACM
Processor design for portable systems
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Synthesis of application-specific memories for power optimization in embedded systems
Proceedings of the 37th Annual Design Automation Conference
A 100-GOPS Programmable Processor for Vehicle Vision Systems
IEEE Design & Test
IEEE Transactions on Pattern Analysis and Machine Intelligence
Digital implementation of cellular sensor-computers: Research Articles
International Journal of Circuit Theory and Applications - Special Issue on CNN Technology (Part 2)
Amdahl's Law in the Multicore Era
Computer
3D Integration: Technology and Applications
3D Integration: Technology and Applications
International Journal of Circuit Theory and Applications
Distributed Cooperative Caching: An Energy Efficient Memory Scheme for Chip Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Image quality assessment: from error visibility to structural similarity
IEEE Transactions on Image Processing
A bio-inspired two-layer mixed-signal flexible programmable chip for early vision
IEEE Transactions on Neural Networks
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This paper introduces a vision processing architecture that is directly mappable on a 3D chip integration technology. Due to the aggregated nature of the information contained in the visual stimulus, adapted architectures are more efficient than conventional processing schemes. Given the relatively minor importance of the value of an isolated pixel, converting every one of them to digital prior to any processing is inefficient. Instead of this, our system relies on focal-plane image filtering and key point detection for feature extraction. The originally large amount of data representing the image is now reduced to a smaller number of abstracted entities, simplifying the operation of the subsequent digital processor. There are certain limitations to the implementation of such hierarchical scheme. The incorporation of processing elements close to the photo-sensing devices in a planar technology has a negative influence in the fill factor, pixel pitch and image size. It therefore affects the sensitivity and spatial resolution of the image sensor. A fundamental tradeoff needs to be solved. The larger the amount of processing conveyed to the sensor plane, the larger the pixel pitch. On the contrary, using a smaller pixel pitch sends more processing circuitry to the periphery of the sensor and tightens the data bottleneck between the sensor plane and the memory plane. 3D integration technologies with a high density of through-silicon-vias can help overcome these limitations. Vertical integration of the sensor plane and the processing and memory planes with a fully parallel connection eliminates data bottlenecks without compromising fill factor and pixel pitch. A case study is presented: a smart vision chip designed on a 3D integration technology provided by MIT Lincoln Labs, whose base process is 0.15@mm FD-SOI. Simulation results advance performance improvements with respect to the state-of-the-art in smart vision chips.