A low-power memory hierarchy for a fully programmable baseband processor
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
The design of a smart imaging core for automotive and consumer applications: a case study
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor
Proceedings of the 45th annual Design Automation Conference
IEICE - Transactions on Information and Systems
81.6 GOPS object recognition processor based on a memory-centric NoC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Signal Processing Systems
A hierarchical vision processing architecture oriented to 3D integration of smart camera chips
Journal of Systems Architecture: the EUROMICRO Journal
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New generations of automobiles will include driver assistance systems requiring powerful, low-cost processors to handle video/camera applications and to enable fast, convenient application development. Shrinking feature sizes on processors already in development will bring substantial increases in system speed and functionality.