81.6 GOPS object recognition processor based on a memory-centric NoC

Authors:
Donghyun Kim;Kwanho Kim;Joo-Young Kim;Seungjin Lee;Se-Joong Lee;Hoi-Jun Yoo
Affiliations:
School of Electrical Engineering and Computer Science, Korea Advance Institute of Science and Technology, Daejeon, Korea;School of Electrical Engineering and Computer Science, Korea Advance Institute of Science and Technology, Daejeon, Korea;School of Electrical Engineering and Computer Science, Korea Advance Institute of Science and Technology, Daejeon, Korea;School of Electrical Engineering and Computer Science, Korea Advance Institute of Science and Technology, Daejeon, Korea;School of Electrical Engineering and Computer Science, Korea Advance Institute of Science and Technology, Daejeon, Korea;School of Electrical Engineering and Computer Science, Korea Advance Institute of Science and Technology, Daejeon, Korea
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

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Abstract

For mobile intelligent robot applications, an 81.6 GOPS object recognition processor is implemented. Based on an analysis of the target application, the chip architecture and hardware features are decided. The proposed processor aims to support both task-level and data-level parallelism. Ten processing elements are integrated for the task-level parallelism and single instruction multiple data (SIMD) instruction is added to exploit the data-level parallelism. The Memory-Centric network-on-chip7 (NoC) is proposed to support efficient pipelined task execution using the ten processing elements. It also provides coherence and consistency schemes tailored for 1-to-N and M-to-1 data transactions in a task-level pipeline. For further performance gain, the visual image processing memory is also implemented. The chip is fabricated in a 0.18-µm CMOS technology and computes the key-point localization stage of the SIFT object recognition twice faster than the 2.3 GHz Core 2 Duo processor.