Computer networks
Algorithms for scalable synchronization on shared-memory multiprocessors
ACM Transactions on Computer Systems (TOCS)
DAC '96 Proceedings of the 33rd annual Design Automation Conference
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
Mapping array communication onto FIFO communication - towards an implementation
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Multiprocessor mapping of process networks: a JPEG decoding case study
Proceedings of the 15th international symposium on System Synthesis
Eclipse: Heterogeneous Multiprocessor Architecture for Flexible Media Processing
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
The Cost of Communication Protocols and Coordination Languages in Embedded Systems
COORDINATION '02 Proceedings of the 5th International Conference on Coordination Models and Languages
Design of multi-tasking coprocessor control for Eclipse
Proceedings of the tenth international symposium on Hardware/software codesign
Simulation based deadlock analysis for system level designs
Proceedings of the 42nd annual Design Automation Conference
Verifying LOC based functional and performance constraints
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Performance guarantees by simulation of process
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Verification approach of metropolis design framework for embedded systems
International Journal of Parallel Programming
SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
Cache aware mapping of streaming applications on a multiprocessor system-on-chip
Proceedings of the conference on Design, automation and test in Europe
81.6 GOPS object recognition processor based on a memory-centric NoC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Systems Architecture: the EUROMICRO Journal
Hi-index | 0.00 |
This paper describes the implementation of a data-synchronization scheme that can be used in the functional description and hardware realization of algorithms for heterogeneous multi-processor architectures. In this scheme, synchronization primitives are chosen such that they can be implemented efficiently in both hardware and software on distributed shared memory architectures, without the need for atomic semaphore instructions. The proposed solution is flexible as the configuration of the data synchronization is programmable even after a hardware realization. It is also scalable since it can be implemented without the need for central resources. We show with experiments that distributed implementations are needed for scalable and high performance systems-on-a-chip.