Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
Bounded scheduling of process networks
Bounded scheduling of process networks
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems
Proceedings of the 14th international symposium on Systems synthesis
Real-Time Systems: Design Principles for Distributed Embedded Applications
Real-Time Systems: Design Principles for Distributed Embedded Applications
Transaction level modeling: flows and use models
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Experimental analysis of the fastest optimum cycle ratio and mean algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient performance analysis of asynchronous systems based on periodicity
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
Performance guarantees by simulation of process
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Efficient Computation of Buffer Capacities for Cyclo-Static Real-Time Systems with Back-Pressure
RTAS '07 Proceedings of the 13th IEEE Real Time and Embedded Technology and Applications Symposium
IEEE Transactions on Signal Processing
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Dataflow models for shared memory access latency analysis
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Journal of Systems Architecture: the EUROMICRO Journal
Hi-index | 0.00 |
Soft real-time applications that process data streams can often be intuitively described as dataflow process networks. In this paper we present a novel analysis technique to compute conservative estimates of the required buffer capacities in such process networks. With the same analysis technique scheduler settings can be verified. Unlike many other soft real-time analysis techniques, it is guaranteed that the desired throughput is obtained for the input stream that is used to characterize the application. Experiments with artificial test-cases indicate that the computed FIFO capacities become more conservative if the desired throughput gets closer to the maximum throughput. The run-time of our algorithm for an H263 video decoder test-case was 14 seconds.