Verifying LOC based functional and performance constraints

Authors:
Xi Chen;H. Hsieh;F. Balarin;Y. Watanabe
Affiliations:
California Univ., Riverside, CA, USA;California Univ., Riverside, CA, USA;Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA;Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Venue:
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Year:
2003

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Abstract

In the era of billion-transistor design, it is critical to establish effective verification methodologies from the system level all the way down to the implementations. Assertion languages (e.g. IBM's Sugar2.0, Synopsys's OpenVera) have gained wide acceptance for specifying functional properties for automatic validation. They are, however, based on linear temporal logic (LTL), and hence have certain limitations. Logic of constraints (LOC) was introduced for specifying quantitative performance constraints, and is particularly suitable for automatic transaction level analysis. We analyze LTL and LOC, and show that they have different domains of expressiveness. Using both LTL and LOC can make the verification process more effective in the context of simulation assertion checking as well as formal verification. Through industrial case studies, we demonstrate the usefulness of this verification methodology.