The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Communication refinement in video systems on chip
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems
Proceedings of the 14th international symposium on Systems synthesis
On the Verification of Temporal Properties
Proceedings of the IFIP TC6/WG6.1 Thirteenth International Symposium on Protocol Specification, Testing and Verification XIII
Constraints Specification at Higher Levels of Abstraction
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Verifying LOC based functional and performance constraints
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic of constraints: a quantitative performance and functional constraint formalism
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dynamic resource reallocation between deployment components
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Validating timed models of deployment components with parametric concurrency
FoVeOOS'10 Proceedings of the 2010 international conference on Formal verification of object-oriented software
Models of Rate Restricted Communication for Concurrent Objects
Electronic Notes in Theoretical Computer Science (ENTCS)
Hi-index | 0.00 |
In this paper, we focus on the verification approach of Metropolis, an integrated design framework for heterogeneous embedded systems. The verification approach is based on the formal properties specified in Linear Temporal Logic (LTL) or Logic of Constraints (LOC). Designs may be refined due to synthesis or be abstracted for verification. An automatic abstraction propagation algorithm is used to simplify the design for specific properties. A user-defined starting point may also be used with automatic propagation. Two main verification techniques are implemented in Metropolis: the formal verification utilizing the model checker Spin and the simulation trace checking with automatic generated checkers. Translation algorithms from specification models to verification models, as well as algorithms of generated checkers are discussed. We use several case studies to demonstrate our approach for verification of system level designs at multiple levels of abstraction.