Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Smart Memories: a modular reconfigurable architecture
Proceedings of the 27th annual international symposium on Computer architecture
Proceedings of the 38th annual Design Automation Conference
A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems
Proceedings of the 14th international symposium on Systems synthesis
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
Multiprocessor mapping of process networks: a JPEG decoding case study
Proceedings of the 15th international symposium on System Synthesis
Synthesis of Embedded Software from Synchronous Dataflow Specifications
Journal of VLSI Signal Processing Systems
Platform-Based Design and Software Design Methodology for Embedded Systems
IEEE Design & Test
System Design: Traditional Concepts and New Paradigms
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
Proceedings of the 30th annual international symposium on Computer architecture
System Design Using Kahn Process Networks: The Compaan/Laura Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Experimental analysis of the fastest optimum cycle ratio and mean algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Schedulability analysis of applications with stochastic task execution times
ACM Transactions on Embedded Computing Systems (TECS)
An automated exploration framework for FPGA-based soft multiprocessor systems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Chip multiprocessing and the cell broadband engine
Proceedings of the 3rd conference on Computing frontiers
Combining simulation and formal methods for system-level performance analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 43rd annual Design Automation Conference
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Multi-processor system design with ESPAM
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs
Journal of Systems Architecture: the EUROMICRO Journal
The Impact of Higher Communication Layers on NoC Supported MP-SoCs
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Proceedings of the conference on Design, automation and test in Europe
Probabilistic design of multimedia embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 44th annual Design Automation Conference
Decoupling of Computation and Communication with a Communication Assist
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Communication between nested loop programs via circular buffers in an embedded multiprocessor system
SCOPES '08 Proceedings of the 11th international workshop on Software & compilers for embedded systems
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Diastolic arrays: throughput-driven reconfigurable computing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Requirements on the execution of Kahn process networks
ESOP'03 Proceedings of the 12th European conference on Programming
A predictable communication assist
Proceedings of the 7th ACM international conference on Computing frontiers
Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking
Proceedings of the Conference on Design, Automation and Test in Europe
Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
A methodology for automated design of hard-real-time embedded streaming systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Systems Architecture: the EUROMICRO Journal
ASP-based optimized mapping in a simulink-to-MPSoC design flow
Journal of Systems Architecture: the EUROMICRO Journal
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Future embedded systems demand multi-processor designs to meet real-time deadlines. The large number of applications in these systems generates an exponential number of use-cases. The key design automation challenges are designing systems for these use-cases and fast exploration of software and hardware implementation alternatives with accurate performance evaluation of these use-cases. These challenges cannot be overcome by current design methodologies which are semi-automated, time consuming and error prone. In this paper, we present a fully automated design flow to generate communication assist (CA) based multi-processor systems (CA-MPSoC). A worst-case performance model of our CA is proposed so that the performance of the CA-based platform can be analyzed before its implementation. The design flow provides performance estimates and timing guarantees for both hard real-time and soft real-time applications, provided the task to processor mappings are given by the user. The flow automatically generates a super-set hardware that can be used in all use-cases of the applications. The software for each of these use-cases is also generated including the configuration of communication architecture and interfacing with application tasks. CA-MPSoC has been implemented on Xilinx FPGAs for evaluation. Further, it is made available on-line for the benefit of the research community and in this paper, it is used for performance analysis of two real life applications, Sobel and JPEG encoder executing concurrently. The CA-based platform generated by our design flow records a maximum error of 3.4% between analyzed and measured periods. Our tool can also merge use-cases to generate a super-set hardware which accelerates the evaluation of these use-cases. In a case study with six applications, the use-case merging results in a speed up of 18 when compared to the case where each use-case is evaluated individually.